1. Field of the Invention
This invention relates to a semiconductor integrated circuit device having a power supply voltage lowering circuit for lowering a power supply voltage from the external and supplying the lowered voltage to an internal circuit, and is particularly suitable for a logic LSI such as a microprocessor or DRAM.
2. Description of the Related Art
In a semiconductor integrated circuit device such as a DRAM, since the withstand voltage of the gate insulative film of a MOS transistor is lowered and the resistance to hot carriers is degraded when it is further miniaturized, it becomes necessary to lower the power supply voltage. However, since the whole system must be changed in order to lower the power supply voltage itself which is supplied to the chip, it becomes a common practice to hold the voltage of the system at 5V as in the conventional case and use a voltage obtained by lowering the power supply voltage supplied from the exterior in the chip in the case of 16-Mbit DRAM.
On the other hand, in the case of 64-Mbit DRAM, the power supply voltage VCC for the whole system is lowered to 3.3V, but the power supply voltage lowering circuit is widely used in the chip. The reason is to make the power consumption as small as possible or enlarge the operation margin of the internal circuit and input characteristic for the power supply voltage VCC and is different from the demand for the 16-Mbit DRAM, but it is considered that the power supply voltage lowering circuit will be widely used not only in the DRAM but also in the semiconductor integrated circuit device.
As the conventional power supply voltage lowering circuit, a feedback type circuit including a P-channel MOS transistor as shown in FIG. 1 and a source follower type circuit including an N-channel MOS transistor as shown in FIG. 2 are known. The basic construction of the former power supply voltage lowering circuit is described in, for example, 1986 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS pp. 272 and 273, Furuyama et al. xe2x80x9cAn Experimental 4Mb CMOS DRAMxe2x80x9d.
The power supply voltage lowering circuit shown in FIG. 1 creates an internal power supply voltage VDD by lowering a power supply voltage VCC supplied from the exterior and includes P-channel MOS transistors T1 to T4, N-channel MOS transistors T5 to T8, and resistors R1, R2. The sources of the MOS transistors T5 and T6 are connected together and the MOS transistors T1 and T2 which are connected in a current mirror configuration are connected between the power supply node VCC and the respective drains of the MOS transistors T5 and T6. The drain-source paths of the MOS transistors T7, T8 are serially connected between the source common connection node of the MOS transistors T5, T6 and the ground node GND. The drain of the MOS transistor T3 is connected to the drain common connection node of the MOS transistors T2, T6 and the source thereof is connected to the power supply node VCC. Further, the gate of the MOS transistor T4 is connected to the drain common connection node of the MOS transistors T2, T6 and the source thereof is connected to the power supply node VCC. The resistors R1 and R2 are serially connected between the drain of the MOS transistor T4 and the ground node GND. The gate of the MOS transistor T5 is connected to the connection node between the resistors R1 and R2 and is applied with a potential VR created by dividing an output potential VDD.
The gate of the MOS transistor T6 is applied with a reference potential VREF and the gates of the MOS transistors T3, T7 are supplied with an operation control signal ACT for determining whether the power supply voltage lowering circuit should be operated or not. The operation control signal ACT is set at a high level when the power supply voltage lowering circuit is operated and is set to a low level when the operation thereof is interrupted, and when the power supply voltage lowering circuit is used in a DRAM, for example, the signal ACT is set at a high level in the operative mode and set at a low level in the standby mode. The gate of the MOS transistor T8 is supplied with a signal VCON for driving the MOS transistor T8 as a constant current source. The signal VCON is a constant potential set at an intermediate level between the power supply potential VCC and the ground potential GND. The internal power supply potential VDD obtained by lowering the power supply potential VCC is derived from the connection node between the drain of the MOS transistor T4 and the resistor R1.
The circuit shown in FIG. 1 keeps the output potential VDD at a constant level by comparing the potential VR with the reference potential VREF in the CMOS current mirror type comparing circuit constructed by the MOS transistors T1, T2, T5 to T8 and controlling the MOS transistor T4 according to the result of comparison. In a case where the internal power supply potential VDD is lower than a preset potential, that is, when VR less than VREF, the MOS transistor T4 is set to the ON state to raise the output potential VDD, and when VR greater than VREF, the MOS transistor T4 is set to the OFF state to lower the output potential VDD.
FIG. 3 shows the relation between the output potential VDD of the power supply voltage lowering circuit and the external power supply potential VCC. In FIG. 3, it is ideal if xe2x80x9cVDD=VCCxe2x80x9d when VCC less than 3.5V as indicated by a one-dot-dash line, but in practice, the driving ability of the P-channel MOS transistor T4 is not so large since the size of the P-channel MOS transistor T4 is limited (when it is made excessively large, the delay time in the feedback loop including the current mirror circuit in the case of xe2x80x9cVCC greater than 3.5Vxe2x80x9d becomes too long and the operation becomes unstable) and the potential applied to the gate of the MOS transistor T4 is an output directly derived from the current mirror circuit and is not set at the GND level, and the relation of xe2x80x9cVDD less than VCCxe2x80x9d is obtained as indicated by the solid line. Further, in the feedback type voltage lowering circuit including the P-channel MOS transistor, the feedback operation is effected and the output potential will oscillate in some condition, and therefore, fine adjustment by phase compensation, for example, is required, thereby making the circuit design difficult. In addition, since the feedback time constant is not limitlessly small, it cannot respond to a rapid variation in the internal potential and noise will be generated.
On the other hand, the power supply voltage lowering circuit of FIG. 2 is a source follower type circuit using an N-channel MOS transistor T10. An internal power supply voltage VDD output from the source of the voltage lowering MOS transistor T10 of N channel type is controlled to xe2x80x9cVPPxe2x88x92VTH (VTH is a threshold voltage of the N-channel MOS transistor T10)xe2x80x9d by applying a high potential VPP to the gate of the MOS transistor T10 and applying an external power supply potential VCC to the drain thereof. Since the power supply voltage lowering circuit of source follower type using the N-channel MOS transistor T10 has no defects of oscillation and through current which are caused in the feedback type circuit, the MOS transistor size can be made sufficiently large, the response to the internal load is good, and the circuit characteristic is excellent. Further, by dispersedly arranging the N-channel MOS transistor T10 in the chip, degradation in the AC characteristic due to an IR drop caused by a resistance between the VDD generation circuit and the actual load circuit will not occur and an excellent response characteristic can be attained.
However, the power supply voltage lowering circuit of source follower type has an essential defect that the internal potential will be made significantly higher than an original preset value in a standby state in which almost no load current flows. Further, even in a state other than the standby state, if the load current becomes small, the internal potential tends to rise. Therefore, if the voltage lowering circuit is used in a DRAM, for example, the internal power supply potential has a dependency on the cycle time tRC, that is, cycle time of {overscore (RAS)} and it is not desirable (the internal power supply potential becomes higher as the cycle time becomes longer).
FIG. 4 shows the above state, and since the abscissa indicates the reciprocal of tRC, xe2x80x9c0xe2x80x9d on the abscissa indicates the standby state. As is clearly seen from FIG. 4, the potential is set to a potential level significantly higher than an original preset value in the standby state. The above problem can be solved by providing an adequate current path so as to always pass a load current in the standby state between the output terminal of internal power supply potential VDD and the ground node GND. However, the current required in the standby state is set to as large as several mA since the channel width of the N-channel MOS transistor T10 acting as the voltage lowering circuit is as large as 104 xcexcm or more, and therefore, the above measure cannot be taken for the DRAM in which the standby current is required to be suppressed to 100 xcexcA or less.
Of course, when the cycle time becomes longer, the power consumption is reduced (the power consumption varies inversely with the cycle time) and no influence is given to the electric power evaluated in the worst condition of the minimum cycle time, and therefore, a problem that the power consumption increases will not occur. Further, in a device such as a DRAM which is set into the standby state by setting a {overscore (RAS)} signal to a high level, even if the internal power supply potential rises in the standby state and VILmax (the maximum input signal level of an input signal which an input buffer can sense as a high level input signal) rises in the input buffer for {overscore (RAS)} including the P-channel MOS transistors T11, T12 and N-channel MOS transistors T13 to T16 shown in FIG. 5, it is not difficult for the device to be set into the active state and no problem occurs. If the device starts to be operated in response to a {overscore (RAS)} signal, a large current is caused to flow in the internal load so that the internal potential will be rapidly lowered to the preset potential and no problem occurs. However, the power supply voltage lowering circuit of source follower type using the N-channel MOS transistor has the following four problems (a) to (d) when it is used in a DRAM.
(a) The device is set into the standby state when {overscore (RAS)} is set to a high level, and after a while, the internal power supply potential VDD starts to rise and VIHmin (the minimum input signal level of an input signal which the input buffer can sense as a high level input signal) of {overscore (RAS)} rises. Then, the {overscore (RAS)} buffer senses an input signal which has been sensed as a high level signal as a low level signal and the device is set into the active state. As a result, since the internal potential is lowered and VIHmin is lowered again, the input buffer senses {overscore (RAS)} as a high level signal and is set into the standby state. Then, after a short period of time, the internal power supply potential VDD starts to rise and VIHmin of {overscore (RAS)} rises. Then, it is set into the active state again. If the operation is repeatedly effected, the oscillation occurs.
(b) In a DRAM having a self-refresh mode, the standby state may be sometimes kept set for a long time in the chip while {overscore (RAS)} is kept at a low level. At this time, the internal power supply potential VDD rises in some cases although {overscore (RAS)} is set at the low level. In this case, there occurs a possibility that the self-refresh mode cannot be reset when VIHmin is raised even if {overscore (RAS)} is set back to the high level to set the device into a mode from the self-refresh mode.
(c) For example, in a case where {overscore (RAS)}, {overscore (CAS)} are continuously output for a long time in the active state in the normal read operation, the current consumption in the internal circuit becomes substantially xe2x80x9c0xe2x80x9d and the internal power supply potential VDD gradually rises. Then, there occurs a possibility that such a long cycle cannot be interrupted when VIHmin is raised even if {overscore (RAS)} is raised to interrupt the long cycle.
(d) In a case where the bit line precharge potential VBL is created based on the internal potential by using half the internal potential of the chip, for example, the potential VBL also rises when the standby state is kept for a long time. In this case, since the impedance of the bit line precharge potential generating circuit is not so large, the bit line precharge potential VBL is kept at a level higher than the preset value for a while after the active state is set, and therefore, the readout margin of the memory cell is reduced and an error may occur.
In any case of the above problems (a) to (d), the above problem will not occur if the {overscore (RAS)} input buffer and the bit line precharge potential generating circuit are designed to be driven by an external power supply voltage. However, if they are so designed, it makes no sense to omit the dependency of the input characteristic on the external power supply potential VCC and the operation margin for the external power supply potential VCC is reduced accordingly, thereby reducing the effect obtained by using the power supply voltage lowering circuit.
The conventional semiconductor integrated circuit device having, as described above, a power supply voltage lowering circuit of feedback type including a P-channel MOS transistor has a problem that the output potential of the voltage lowering circuit falls below a preset value (ideal value) when a current abruptly flows through the load while the external power supply potential is low. Further, there occurs a problem that the circuit design is difficult and noise is generated. Further, the conventional semiconductor integrated circuit device having a source follower type power supply voltage lowering circuit including an N-channel MOS transistor has a problem that the internal power supply potential is raised to a level significantly higher than an original preset level in the standby state in which almost no load current flows.
Accordingly, a first object of this invention is to provide a semiconductor integrated circuit device which has a power supply voltage lowering circuit and in which the output potential of the power supply voltage lowing circuit is prevented from lowing below a preset value when a current abruptly flows through the load while the external power supply potential is low, simplifying the design and suppressing generation of noise.
A second object of this invention is to provide a semiconductor integrated circuit device capable of solving a problem caused when the internal power supply potential rises in the standby state.
A third object of this invention is to provide a semiconductor memory device which has a power supply voltage lowering circuit and in which the output potential of the power supply voltage lowing circuit is prevented from lowing below a preset value when a current abruptly flows through the load while the external power supply potential is low, simplifying the design and suppressing generation of noise.
A fourth object of this invention is to provide a semiconductor memory device capable of solving a problem caused when the internal power supply potential rises in the standby state.
A fifth object of this invention is to provide a microprocessor which has a power supply voltage lowering circuit and in which the output potential of the power supply voltage lowing circuit is prevented from lowing below a preset value when a current abruptly flows through the load while the external power supply potential is low, simplifying the design and suppressing generation of noise.
A sixth object of this invention is to provide a microprocessor capable of solving a problem caused when the internal power supply potential rises in the standby state.
The first and second objects of this invention can be attained by a semiconductor integrated circuit device comprising a first voltage lowering circuit of source follower type having an N-channel MOS transistor for lowering a power supply voltage supplied from the exterior and supplying the lowered voltage to at least part of an internal circuit as a power supply voltage thereof; an inverter type input buffer; and a second voltage lowering circuit of feedback type having a P-channel MOS transistor exclusively used for supplying a potential created by lowering the power supply voltage supplied from the exterior to the inverter type input buffer as a power supply voltage thereof.
With the above construction, since the feedback type voltage lowering circuit having the P-channel MOS transistor exclusively used for the inverter type input buffer in which a load current is extremely small is used, the stable operation can be realized without exhibiting the defect of the feedback type voltage lowering circuit. Therefore, a semiconductor integrated circuit device can be provided in which the output potential of the power supply lowering circuit is prevented from lowering below a preset value when a current abruptly flows through the load while the external power supply potential is low, the design can be made simple, and generation of noise can be suppressed. Further, since the source follower type voltage lowering circuit having the N-channel MOS transistor is not used for the inverter type input buffer, a semiconductor integrated circuit device can be provided in which a problem occurring when the internal power supply potential rises in the standby state can be avoided.
The third and fourth objects of this invention can be attained by a semiconductor memory device comprising a dynamic memory cell array; a row circuit for selecting a row of the memory cell array; a column circuit for selecting a column of the memory cell array; a write circuit for writing data into the memory cell array; a {overscore (RAS)} buffer for supplying an input {overscore (RAS)} signal to the row circuit; a {overscore (CAS)} buffer for supplying an input {overscore (CAS)} signal to the column circuit; a {overscore (WE)} buffer for supplying an input {overscore (WE)} signal to the write circuit; a first voltage lowering circuit of feedback type having a P-channel MOS transistor exclusively used for supplying a potential created by lowering the power supply voltage supplied from the exterior to at least one of the {overscore (RAS)} buffer, {overscore (CAS)} buffer and {overscore (WE)} buffer as the power supply voltage thereof; a bit line precharge potential generating circuit for generating a precharge potential of bit lines of the memory cell array; a memory cell plate potential generating circuit for generating a plate potential of memory cells of the memory cell array; and a second voltage lowering circuit of feedback type having a P-channel MOS transistor exclusively used for supplying a potential created by lowering the power supply voltage supplied from the exterior to part of at least one of the bit line precharge potential generating circuit and the memory cell plate potential generating circuit as a power supply voltage thereof.
With the above construction, since the first exclusive voltage lowering circuit of feedback type having the P-channel MOS transistor is used for at least one of the {overscore (RAS)} buffer, {overscore (CAS)} buffer and {overscore (WE)} buffer in which a load current is extremely small and the second exclusive voltage lowering circuit of feedback type having the P-channel MOS transistor is provided for part of at least one of the bit line precharge potential generating circuit and the memory cell plate potential generating circuit, the stable operation can be realized without exhibiting the defect of the feedback type voltage lowering circuit. Therefore, a semiconductor memory device can be provided in which the output potential of the power supply lowering circuit is prevented from lowering below a preset value when a current abruptly flows through the load while the external power supply potential is low, the design can be made simple, and generation of noise can be suppressed. Further, since the source follower type voltage lowering circuit having the N-channel MOS transistor is not used for the {overscore (RAS)} buffer, {overscore (CAS)} buffer, {overscore (WE)} buffer, bit line precharge potential generating circuit and memory cell plate potential generating circuit, a semiconductor memory device can be provided in which a problem occurring when the internal power supply potential rises in the standby state can be avoided.
Further, the fifth and sixth objects of this invention can be attained by a microprocessor comprising a first input buffer of inverter type to which data and an instruction are input; an instruction register for storing an instruction input to the first input buffer; a program counter to which an operand address of an instruction input to the instruction register is input; a first output buffer operated on a power supply voltage supplied from the exterior, for receiving a memory address output from the program counter via an address bus and outputting the memory address to the exterior; a stack pointer for specifying a stack on the memory; a second input buffer for receiving a timing signal input from the exterior; a second output buffer operated on a power supply voltage supplied from the exterior, for outputting the timing signal to the exterior; a control circuit supplied with an operation code of an instruction input to the instruction register and a timing signal input to the second input buffer, for controlling the program counter and stack pointer and outputting the timing signal to the second output buffer; an ALU for receiving data input to the first input buffer via a data bus at one input terminal thereof and outputting the result of operation to the data bus; an accumulator for accumulating data input from the address bus and supplying accumulated data to the other input terminal of the ALU; a third output buffer operated on a power supply voltage supplied from the exterior, for outputting data on the data bus to the exterior; a first voltage lowering circuit of feedback type having a P-channel MOS transistor exclusively used for supplying a potential created by lowering the power supply voltage supplied from the exterior to the first and second input buffers as power supply voltages thereof; and a second voltage lowering circuit of source follower type having an N-channel MOS transistor exclusively used for supplying a potential created by lowering the power supply voltage supplied from the exterior to the instruction register, control circuit, program counter, stack pointer, ALU and accumulator as power supply voltages thereof.
In the above microprocessor, since a large current is not required in the first and second input buffers even in the active state, the exclusive voltage lowering circuit of feedback type in which the stability in the feedback loop can be attained and the high level stability can be attained in the standby mode is used. Since the first to third output buffers require a large current, they are operated on a power supply voltage supplied from the exterior. Further, in the other internal circuits, that is, the control circuit, instruction register, ALU, accumulator, stack pointer and program counter, the second voltage lowering circuit of source follower type having the exclusive N-channel MOS transistor in which an adequate amount of current flows and the operation is stable is used. As a result, a microprocessor can be provided in which the output potential of the power supply lowering circuit is prevented from lowering below a preset value when a current abruptly flows through the load while the external power supply potential is low, the design can be made simple, and generation of noise can be suppressed. Further, since the voltage lowering circuit of source follower type having the N-channel MOS transistor is not used for the input buffer, a microprocessor in which a problem caused when the internal power supply potential rises in the standby state can be avoided can be obtained.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.